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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:46:29 11/12/2006 
-- Design Name: 
-- Module Name:    contador5 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity contador5 is
    Port ( clk : in  STD_LOGIC;
           cuenta : out  STD_LOGIC_VECTOR (4 downto 0));
end contador5;

architecture Behavioral of contador5 is
	signal cuenta_int	: std_logic_vector(4 downto 0) := (others => '0');
begin
	
	P1: process (clk)
	begin
		if (clk = '1' and clk'event) then cuenta_int <= cuenta_int+1;
		end if;
	end process;
	cuenta <= cuenta_int;
end Behavioral;

